Annmol Cherian, Ajay Augustine, Vinod Pangracious and Jemy Jose, Rajagiri School of engineering & technology, India

Moore's law describes a long-term trend in the history of computing hardware. The conventional methods have reached his limits so new fields has to be exploited. Such a concept is 3-Dimensional integration where the components are arranged in 3D plane. This arrangement can increase the package density of devices. The successful construction of 3D memory can lead to a new revolution in designing and manufacturing high performance microprocessor system on chip. The major problem is the increased temperature effects. It’s important to develop an accurate power profile extraction methodology to design 3D memory. The total power dissipation includes static and dynamic component. In this paper the static power dissipation of the memory cell is analysed and is used to accurately model the inter-layer thermal effects for 3D memory stack. Then packaging of the chip is considered and modelled using an architecture level simulator. This modelling is intended to analyse the thermal effects of 3D memory, its reliability and lifetime of the chip with greater accuracy.

3D integration, 3Dmemory, Thermal effects