Saleh Abdel-Hafeez^{1, 2}, Sanabel Otoom¹ and Muhannad Quwaider¹, ¹Jordan University of Science and Technology, Jordan, ²Sabbatical at Qassim University, Saudi Arabia

Memory Alias Table exploits a major role in Register Renaming Unit (RRU) for maintaining the translation between logical registers to physical registers for the given instruction(s). This work presents the design of the memory Alias Table based on the 8TCell with multiport write, read, and content-addressable operation for 2-WAY three operands machine cycle. Results show that four read ports operate simultaneously within a half-cycle, while two-write ports operate simultaneously within the other half-cycle. The operation of content-addressable with two parallel ports is managed during the half-cycle of the read phase; thus, the three operations occur within a single cycle without latency. HSPICE simulations conduct 32-rows x 6-bit with 21T-Cell memory Alias Table that has 4- read ports, 2-write ports, and 2-content-addressable ports using a standard 65 nm/1V CMOS process. Simulations reveal that the proposed design operates within a one-cycle of 1 GHz consuming an average power of 0.87 mW

Content-Addressable,8T-Cell SRAM, 2-WAY Instructions Cycle, Memory Alias Table, Register Renaming Unit.