Nasrin Imanpour¹ and Sayed Ahmad Salehi², ¹University of South Carolina, USA, ²University of Kentucky, USA

Stochastic computing (SC) provides a fault-tolerant and low-cost alternative to conventional binary computing (BC). The capacity of SC to implement complex mathematical functions with simple logic gates creates a path toward the design of efficient hardware architectures. This paper presents a new methodology for the hardware implementation of servomotor controller using SC. We design SC circuits using both quadrature decoder and efficient decoder for implementing servo controller and compare them with traditional BC-based servo controller. The quadrature decoder requires more hardware resources than efficient decoder but can provide position information in PWM form. The FPGA implementation result shows that, compared to BC-based design, quadrature decoder-based design achieves 56.7% savings in area and 33.33% savings in power consumption, and efficient decoder-based design achieves 73.7% savings in area and 33.33% savings in power consumption.

Stochastic computing (SC), servomotor controller, quadrature decoder, efficient decoder, stochastic integrator.