Sowmya K B , Neha J C , Preeti Yadav , Paridhi Sudarshan and Shreya V Sanoj , RV College of Engineering, India

This work presents the design, modelling, and synthesis of SoC, a compact RISCV based SoC integrating three IP cores: RVMYTH processor, an 8x Phase-Locked Loop for clock generation, and a 10-bit Digital-to-Analog Converter for analog interfacing. The SoC was developed using open-source tools and Sky130 technology, demonstrating feasibility for educational and practical applications in embedded systems, IoT devices, and digital signal processing. The design flow encompasses RTL modelling, synthesis using Yosys, and timing verification with OpenSTA. The RVMYTH core, converted from TL-Verilog, was integrated with analog IP models and validated through pre-synthesis and post-synthesis simulations using iverilog and GTKwave. The synthesized netlist comprises 5,552 cells occupying 58,173.29 um². Static timing analysis confirmed all constraints were met, achieving 0.86 ns positive slack with a maximum path delay of 10.01 ns. The application-oriented design makes the SoC suitable for IoT sensor nodes, industrial control systems, audio processing, and motor control applications. The integrated DAC enables direct sensor/actuator interfacing, while the RISC-V architecture supports custom instruction extensions for domain-specific applications. The PLL ensures clock stability critical for serial communication interfaces and real-time control.

RISC-V processor, Phase-Locked Loop (PLL), Digital-to-Analog Converter (DAC),OpenLANE, Sky130 PDK