S. Valarmathi¹, R. Vani² and M. Sangeetha¹, ¹Karpaga Vinayaga College of Engg. and Technology, India and ²Anna University of Technology, India

This paper proposes about motion estimation in H.264/AVC encoder. Compared with standards such as MPEG-2 and MPEG-4 Visual, H.264 can deliver better image quality at the same compressed bit rate or at a lower bit rate. The increase in compression efficiency comes at the expense of increase in complexity, which is a fact that must be overcome. An efficient Co-design methodology is required, where the encoder software application is highly optimized and structured in a very modular and efficient manner, so as to allow its most complex and time consuming operations to be offloaded to dedicated hardware accelerators. The Motion Estimation algorithm is the most computationally intensive part of the encoder which is simulated using MATLAB. The hardware/software co-simulation is done using system generator tool and implemented using Xilinx FPGA Spartan 3E for different scanning methods.

H.264/AVC, Hardware accelerators, Motion Estimation, Scanning methods.