Navdeep Prashar and Balwinder Singh, C-DAC, India

The coordinate rotation digital computer (CORDIC) algorithm is well known iterative algorithm for performing rotations in digital signal processing applications. Hardware implementation of CORDIC results increase in Critical path delay. Pipelined architecture is used in CORDIC to increase the clock speed and to reduce the Critical path delay. In this paper a hardware efficient Digital sine and cosine wave generator is designed and implemented using Pipelined CORDIC architecture. FPGA based architecture is presented and design has been implemented using Xilinx 12.3 device.

CORDIC, FPGA, Pipelined architecture, Micro -rotations.