Anusuya Yuvaraj and R. C. Biradar, Reva Institute of Technology and Management, India

During the test mode of flip flop in a chip, a set of input vectors are sent through the flip-flop, itconsumes more power consumption than in the normal functional mode. In this paper, we propose a latch with bi -stable element which reduces area as well as the power consumed. The latch proposed consists of simple basic gates involving two inverters back to back which acts as a bi-stable element and a transmission gate with the clock signal used to enable and disable the rest of the circuit with impact on running the latch on Static Timing Analysis. The input test vectors are either given by Automatic Test Pattern Generation (ATPG) or many other methods. We model this using T-Simulation Program with Integrated Circuit Emphasis (T-SPICE) and see the power consumed.

Scan Chain, Latch, Bi-stable element, ATPG, Flip-Flops