Karthik Reddy.G and Kavita Khare, Maulana Azad National Institute of Technology, India

Full adder circuit is functional building block of micro processors, digital signal processors or any ALUs. In this paper leakage power is reduced by using less number of transistors with the techniques like GDI (Gate Diffusion Input) and PTL (Pass Transistor Logic) techniques. In this paper 3 designs have been proposed of low power 1 bit full adder circuit with 10Transistors ( using PTL multiplexer) , 8 Transistor (by using NMOS and PMOS PTL devices), 12Transistors (6Transistors to generate carry using GDI technique and 6Transistors to generate sum using tri state inverters). These circuits consume less power with maximum of 73% power saving com-pare to conventional 28T design. The proposed circuit exploits the advantage of GDI technique and pass transistor logic, and sum is generated by tri state inverter logic in all designs. The entire simulations have been done on 180nm single n-well CMOS bulk technology, in virtuoso platform of cadence tool with the supply voltage 1.8V and frequency of 100MHz.

leakage power, GDI, Pass transistor logic, tri-state inverters.