Varun Nehru and H.S. Jattana, VLSI Design Division, India

This paper presents a unified architecture design of the RSA cryptosystem i.e. RSA crypto-accelerator along with key-pair generation. A structural design methodology for the same is proposed and implemented. The purpose is to design a complete cryptosystem efficiently with reduced hardware redundancy. Individual modular architectures of RSA, Miller-Rabin Test and Extended Binary GCD algorithm are presented and then they are integrated. Standard algorithm for RSA has been used. The RSA datapath has further been transformed into DPA resistant design. The simulation and implementation results using 180nm technology are shown and prove the validity of the architecture.

RSA, cryptosystem, crypto-accelerator, public key, private key, Extended Binary GCD, Stein, Miller-Rabin, modular inverse, DPA resistance