Thottempudi Pardhu, S. Manusha and K. Sirisha, Marri Laxman Reddy Institute of Technology & Management, India

We present a new design for a 1-bit full adder featuring hybrid-CMOS design style. Our approach achieves low-energy operations in 90nm technology. Hybrid-CMOS design style makes use of various CMOS logic style circuits to build new full adders with desired specifications. The new SERF- full adder (FA) circuit optimized for ultra low power operation is based on modified XOR gates with clock gating to minimize the power consumption. And also generates full-swing outputs simultaneously. The new full-adder circuit successfully operates at low voltages with excellent signal integrity. The new adder displayed better power and delay metrics as compared to the standard full adders. To evaluate the performance of the new full adder in a real circuit, we realized 4-2,5-2,5-3,7-2,11-2,15-4,31-5 compressors which are basically used in multiplier modules of DSP filters. Simulated results using 90nm standarad CMOS technology are provided. The simulation results show a 5% - 20% reduction in power and delay for frequency 50MHz and supply voltages range of 1.1 v.

SERF Full adder, ultra low power