M Suresh¹, A K Panda¹, Mukesh Sukla¹, Marakonda Patnaikuni Vasanthi² and Sowpati Santhi³,
¹NIST, India, ²RGUKT-Telangana, India and ³RGUKT-Andhra Pradesh, India

The low-power consumption with less delay time has become an important issue in the recent trends of VLSI. In these days, the low power systems with high speed are highly preferable everywhere. Designers need to understand how low-power techniques affect performance attributes, and have to choose a set of techniques that are consistent with these attributes .The main objective of this paper is to describe, how to achieve low power consumption with approximately same delay time in a single circuit. In this paper, we make circuits with CMOS and MTCMOS techniques and check out its power and delay characteristics. The circuits designed using MTCMOS technique gives least power consumption. All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.

MTCMOS, sleep mode, leakage current, header switch, footer switch