Shelja A S¹, Nandakumar R² and Muruganantham C¹, ¹NCERC- University of Calicut, India and ²N.I.E.L.I.T, India

An implementation of IEEE 1149.1 TAP controller is presented in this paper. JTAG is an established technology and industry standard for on-chip boundary scan testing of SoCs. JTAG TAP controllers are becoming a delivery and control mechanism for Design For Test. The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications.

IP core; IEEE 1149.1, TAP; TMP controller; JTAG; boundary scan; DFT