Hemanth Kumar Nalajala, Rajesh B, Sivaraman R, Sridevi A, Amirtharajan Rengarajan and Sundararaman Rajagopalan S, SASTRA Deemed to be University, India

Random numbers play a significant role while implementing the crypto architectures on reconfigurable hardware. Chaotic attractors are reliable sources of deterministic random number generation due to their large keyspace capability. Chaos exhibits random perturbations in floating-point units which is a challenge while replicating the system of equations on hardware. The conversion of floating-point numbers to binary representation will take many quantization possibilities which certainly affect the randomness and sensitivity to initial conditions. This work aims to implement the chaotic Rössler attractor based Pseudo Random Number Generation (PRNG) on FPGA through simulation and real time experimentation. This attractor has been realized on Altera Cyclone II EP2C20F484C7 FPGA using hardware primitives. It required 201 LUTs with a power dissipation of 78.48 mW and time duration of 4 µS to generate 32,768 random bits. The randomness of this attractor was evaluated through entropy, correlation, bit distribution and NIST SP 800 – 22 analyses.

Chaos, PRNG, Quantization effects, Reconfigurable Hardware, Rössler attractor, Differential equations & FPGA